VBPS=LOW, ES=LITTLE_ENDIAN_FIRST, CM=IDLE, SDIS=NOT_DISABLED
USB mode (host mode)
| CM | Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 0 (IDLE): Idle 1 (RESERVED): Reserved 2 (DEVICE_CONTROLLER): Device controller 3 (HOST_CONTROLLER): Host controller |
| ES | Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. 0 (LITTLE_ENDIAN_FIRST): Little endian: first byte referenced in least significant byte of 32-bit word. 1 (BIG_ENDIAN_FIRST_BY): Big endian: first byte referenced in most significant byte of 32-bit word. |
| RESERVED | Not used in host mode |
| SDIS | Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved. 0 (NOT_DISABLED): Not disabled 1 (DISABLED_SETTING_TO): Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature. |
| VBPS | VBUS power select 0 (LOW): vbus_pwr_select is set LOW. 1 (HIGH): vbus_pwr_select is set HIGH |
| RESERVED | reserved |